Book and Book Chapters

Book Chapters: 11

11. Ankur Beohar, Ambika Prasad Shah, Nandakishor Yadav, Gopal Raut and Santosh Kumar Vishvakarma, “Design and Analysis of Cyl GAA-TFET-Based Cross-Coupled Voltage Doubler Circuit”, Book Chapter Published under title Microelectronics Circuits and System Lecture Notes in Electrical Engineering, Springer Nature Singapore Pte Ltd, Volume 755, page no 69-79, Sep -2021, Book ISBN: 978-981-16-1570-2.

10. Vaibhav Neema, Priyanka Parihar and Santosh Kumar Vishvakarma, “Design and analysis of ultra-low power memory architecture with MTCMOS asymmetrical ground-gated 7T SRAM cell” Book Chapter Published under title Microelectronics Circuits and System Lecture Notes in Electrical Engineering, Springer Nature Singapore Pte Ltd, Volume 755, page no 123-131, Sep -2021, Book ISBN: 978-981-16-1570-2.

9. Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Abhinav Vishwakarma and S. K. Vishvakarma, "A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell", in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

8. Ankur Beohar, Gopal Raut, Gunjan Rajput, Ambika Prasad Shah, Bhupendra Singh Renewal, Abhinav Vishwakarma and S. K. Vishvakarma, "Compact Spiking Neural Network System with SiGe based Cylindrical Tunneling Transistor for Low Power Applications", in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

7. Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan and S. K. Vishvakarma, "Efficient Low-Precision CORDIC algorithm for Hardware Implementation of Artificial Neural Network", in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

6. Neha Gupta, Tanisha Gupta, Sajid Khan, Gunjan Rajput and S. K. Vishvakarma, "Low Leakage Highly Stable Robust Ultra-Low Power 8T SRAM Cell in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

5. Sajid Khan, Neha Gupta, Abhinav Vishvakarma, Shailesh Singh Chouhan, Jai Gopal Pandey and  S. K. Vishvakarma, "Dual-Edge Triggered Light-Weight Implementation of AES for IoT Security", in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

4. Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey and S. K. Vishvakarma, "An Ultra-Low Power AES Architecture for IoT", in VLSI Design and Test, 23rd International Symposium, VDAT 2019, Indore, India, July 4–6, 2019, Springer-Singapore, Eds. Sengupta A., Dasgupta S., Singh V., Sharma R., Kumar Vishvakarma S., vol. 1066, Book ISBN: 978-981-329-767-8.

3. Ambika Prasad Shah, Nandakishor Yadav and  S. K. Vishvakarma, "LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits", in VLSI Design and Test, 21st International Symposium, VDAT 2017, Roorkee, India, June 29 – July 2, 2017, Springer Singapore. Eds. Kaushik Brajesh K., Dasgupta Sudeb., Singh Virendra, vol. 711, Book ISBN: 978-981-10-7470-7.

2. Bhupendra Reniwal and S. K. Vishvakarma, "Process-Aware Ultra-High-Speed Hybrid Sensing Technique for Low power Near-Threshold SRAM", in VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Springer. Eds. Gaur Manoj Singh, Zwolinski Mark, Laxmi Vijay, Boolchandani Dharmendra, Singh Virendra, Singh Adit D., vol. 382, Book ISBN 978-3-642-42023-8.

1. Chandrabhan Kushwah  and S. K. Vishvakarma, "Ultra-low power Sub-Threshold SRAM Cell Design to Improve Read Static Noise Margin" in VLSI Design and Test, 16th International Symposium on VLSI Design and Test, VDAT 2012, Shipur, India, July 1-4, 2012, Springer, Berlin, Heidelberg. Eds. Rahaman Hafizur, Chattopadhyay Sanatan, Chattopadhyay Santanu, vol. 7373, Book ISBN 978-3-642-31493-3.